Read on Twitter
My read on ADL-
Its a play for area efficiency and big boost in threaded perf at minimal area. The issue is Intel's cost structure. They have substantially larger cores than AMD and dont want to blow up die size too much as that impacts margins and means they need more wafers
1/? https://twitter.com/Cardyak/status/1356610858487529473
Its a play for area efficiency and big boost in threaded perf at minimal area. The issue is Intel's cost structure. They have substantially larger cores than AMD and dont want to blow up die size too much as that impacts margins and means they need more wafers
1/? https://twitter.com/Cardyak/status/1356610858487529473
Willow Cove is 4.29mm/core or 6.11mm with 1.25MB L2. Zen2 3.61mm (+69% vs Zen2) Zen3 is 4.04mm (+51%).
That's an issue when competing against 12-16C Warhol SKUs.
ST/MT tradeoff is tough for Intel here and the best use of their area/power budget is key.
2/?
That's an issue when competing against 12-16C Warhol SKUs.
ST/MT tradeoff is tough for Intel here and the best use of their area/power budget is key.
2/?
In contrast Tremont is tiny .85mm without L2, while boasting roughly Ivy Bridge IPC. With Gracemont we know it finally! has more modern ISA extensions.
Intel hasn't disclosed implementation details of AVX in Gracemont but I'd guess at 2x256bit vectors. If so the additional
3/?
Intel hasn't disclosed implementation details of AVX in Gracemont but I'd guess at 2x256bit vectors. If so the additional
3/?
resources should only add about .125mm. Even if you assume uarch improvements to push IPC closer to Skylake level its easy to imagine core area around 1.5mm.
So 8 Gracemont cores in ADL shouldn't take much space while offering very strong gains in multi-threaded performance.
4/?
So 8 Gracemont cores in ADL shouldn't take much space while offering very strong gains in multi-threaded performance.
4/?
Far more area efficient then adding a few GoldenCove cores. As far as power the idle power benefits are biggest in deep sleep state where Intel already does very well.
There are naturally issues with heterogenous cores. How the hardware guided scheduler has evolved is unknown
5/?
There are naturally issues with heterogenous cores. How the hardware guided scheduler has evolved is unknown
5/?
Current leaks imply your limited to ISA supported by Gracemont thus losing AVX512. I'm a bit dubious as it doesn't seem it'd be that hard to rely on affinity mask. Require affinity set to only big cores to allow process to execute AVX512, and limit process migration as needed
6/?
6/?
How they handle virtualization/cache blocking are also unknown
Longterm maybe BigLittle is a partial solution to speculative vulnerabilities, those are often less design flaws as much as inherent result of speculative/OoOE.
Keep the big cores for perf sensitive content/OS UI
7/?
Longterm maybe BigLittle is a partial solution to speculative vulnerabilities, those are often less design flaws as much as inherent result of speculative/OoOE.
Keep the big cores for perf sensitive content/OS UI
7/?
and pin security conscious apps to the little cores which could be in-order and prevent leaking data.
Provided of course Intel had an in-order core fast to be viable. Intel has moved away from in-order designs & Silvermont/Goldmont are impacted by specter so this is a big if
8/9
Provided of course Intel had an in-order core fast to be viable. Intel has moved away from in-order designs & Silvermont/Goldmont are impacted by specter so this is a big if
8/9
As an addendum, given how memory bandwidth limited 16C Ryzen can be in many ostensibly compute limited workloads, 8+8 isn't a bad option even with DDR5 coming. Cores sitting idle waiting on memory aren't adding a lot of value.
9/9
9/9
